This application claims the priority benefit of Taiwan application Ser. No. 90114254, filed Jun. 13, 2001.
1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a manufacturing process of a MOS transistor.
2. Description of the Related Art
In the related art of the manufacturing process of a MOS transistor, a gate oxide layer and a polysilicon layer are successively formed on a substrate. An annealing is performed in order to enlarge the polysilicon grains within the polysilicon layer. The polysilicon layer is patterned to form a gate. A dopant is doped into the substrate on the two sides of the gate, thereby forming a source/drain region.
However, during the annealing step of the manufacturing process of a MOS transistor in the related art, the polysilicon located near the newly formed grain boundary reacts with the gate oxide and produces volatile SiO, therefore the gate oxide near the grain boundary is damaged and the entire gate oxide layer has an uneven thickness.
When the device gradually increases in integration, the thickness of the ate oxide layer decreases correspondingly. When the gate oxide layer is thinner, the effects of uneven thickness mentioned above become more apparent. For example, if the variation of the thickness ranges from approximately 6 xc3x85 to 10 xc3x85 in the annealing process and the thickness of the gate oxide layer is approximately 100 xc3x85, the degree of variation in the thickness of the gate oxide layer is merely about 10%, thus the device still has enough stability. However, if the thickness of the gate oxide layer is reduced to about 25 xc3x85, the degree of variation in the thickness of the gate oxide layer is increased to about 50%, and the device stability is greatly reduced.
Moreover, during the annealing step in the related art, the dopant located in the gate is very easily driven to the underlying substrate under the dual influence of high temperature and the polysilicon grain enlargement. Therefore, the electrical properties of the device are changed, which makes the device defective and lowers the yields.
The invention provides a manufacturing process of a MOS transistor. A gate dielectric layer and a polysilicon layer are successively formed on a substrate. Nitrogen ions are implanted into the contact region of the polysilicon layer with the dielectric layer. An annealing is performed in order to enlarge the polysilicon grains within the polysilicon layer. The polysilicon layer is patterned to form a gate. A dopant is doped into the substrate on the two sides of the gate, thereby forming a source/drain region.
The invention also provides a manufacturing process of a gate. A gate dielectric layer and a polysilicon layer are successively formed on the substrate. An annealing is performed in order to enlarge the polysilicon grains within the polysilicon layer. The polysilicon layer is patterned to form a gate.
In the manufacturing process of a MOS transistor provided in the present invention, when the annealing is performed to enlarge the grain within the polysilicon layer, the nitrogen implanted suppresses the growth of the grain boundary in the contact region of the polysilicon layer with the gate oxide layer. Therefore, the amount of damage to the gate dielectric layer caused by the grain boundary is effectively reduced, and the gate oxide layer does not become uneven. The degree of variation in the thickness of the gate oxide layer is reduced and device stability is increased.
Moreover, in the manufacturing process of a MOS transistor provided in the present invention, when the annealing is performed to enlarge the polysilicon grains within the polysilicon layer, the dopant within the polysilicon layer does not diffuse into the underlying substrate due to the resistance of the thin nitrogen-containing region at the bottom of the gate. For this reason, changes in the electrical properties of the device are prevented, which increases the yields.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.